// Cell names have been changed in this file by netl_namemap on Mon Jan  3 04:00:09 UTC 2022
//////////////////////////////////////////////////////////////////////////////
//
//  pcs_raw_aon_lane.v
//
//  Raw PCS always-on lane module
//
//  Original Author: Ameer Youssef
//  Current Owner:   Gaurav Dubey
//
//////////////////////////////////////////////////////////////////////////////
//
// Copyright (C) 2013 Synopsys, Inc.  All rights reserved.
//
// SYNOPSYS CONFIDENTIAL - This is an unpublished, proprietary work of
// Synopsys, Inc., and is fully protected under copyright and trade secret
// laws.  You may not view, use, disclose, copy, or distribute this file or
// any information contained herein except pursuant to a valid written
// license agreement. It may not be used, reproduced, or disclosed to others
// except in accordance with the terms and conditions of that agreement.
//
//////////////////////////////////////////////////////////////////////////////
//
//    Perforce Information
//    $Author: gdube $
//    $File: //dwh/up16/main/dev/pcs_raw/dig/rtl/pcs_raw_aon_lane.v $
//    $DateTime: 2019/09/28 22:05:13 $
//    $Revision: #72 $
//
//////////////////////////////////////////////////////////////////////////////

`include "dwc_e12mp_phy_x4_ns_macros.v"
`include "dwc_e12mp_phy_x4_ns_pcs_raw_macros.v"

`timescale 1ns/10fs
module dwc_e12mp_phy_x4_ns_pcs_raw_aon_lane (
// Clocks and resets
input  wire            cr_clk,
input  wire            cr_rst_aon,

input  wire            rx_reset,
input  wire            tx_disable,
input  wire            rx_disable,
input  wire            isolate_en,
input  wire            tx_ack_int,
input  wire            rx_ack_int,
output wire            tx_ack,
output wire            rx_ack,

// Initial power-up done status (from aon_lane register)
output wire            lane_init_pwrup_done_r,
`ifdef DWC_E12MP_X4NS_RX_CDR_PPM_DETECTOR_ADDED
output wire            rx_cdr_detector_dis_in_adapt_r,
output wire            rx_cdr_ppm_monitor_mode_r,
output wire            rx_cdr_detector_en_r,
output wire [11:0]     rx_cdr_recovery_time_r,
`endif

// RX Adaptation Status and Value (to rx_ctl)
output wire [7:0]      rx_att_adpt_val_r,
output wire [9:0]      rx_vga_adpt_val_r,
output wire [2:0]      rx_ctle_pole_adpt_val_r,
output wire [9:0]      rx_ctle_boost_adpt_val_r,
output wire [12:0]     rx_dfe_tap1_adpt_val_r,
output wire [11:0]     rx_dfe_tap2_adpt_val_r,
output wire [11:0]     rx_dfe_tap3_adpt_val_r,
output wire [11:0]     rx_dfe_tap4_adpt_val_r,
output wire [11:0]     rx_dfe_tap5_adpt_val_r,
output wire            rx_adpt_done_r,

// Fast flags (to power-gated lane)
output wire            rx_fast_vco_cal_r,
output wire            rx_fast_vco_wait_r,
output wire            rx_fast_pwrup_r,
output wire            tx_fast_rxdet_r,
output wire            tx_fast_cmn_mode_r,
output wire            tx_fast_sup_r,
output wire            rx_fast_dfe_adapt_r,
output wire            rx_fast_afe_adapt_r,
output wire            rx_fast_iq_cal_r,
output wire            rx_fast_reflvl_cal_r,
output wire            rx_fast_bypass_cal_r,
output wire            rx_fast_dfe_cal_r,
output wire            rx_fast_afe_cal_r,
output wire            rx_fast_adapt_r,
output wire            rx_fast_startup_cal_r,

// Fast flags 2 (to power-gated lane)
output wire [6:0]      rx_fast_flags_rsvd_r,
output wire            rx_fast_cont_afe_cal_r,
output wire            rx_fast_cont_phase_cal_r,
output wire            rx_fast_cont_data_cal_r,
output wire            rx_fast_cont_adapt_r,
output wire            rx_fast_cont_cal_adapt_r,

// Mantis 6866 - Send post-override tx/rx_disables to
// power-gated lanes and PMA
output wire            tx_pma_disable,
output wire            rx_pma_disable,

// ----------------------------------------------------
// Internal from/to other Raw PCS lanes (pcs_raw_lane)
// ----------------------------------------------------
input  wire            lane_cmncal_init_in,
input  wire            lane_cmncal_done_in,
input  wire            lane_disable_in,
output wire            lane_cmncal_init_out,
output wire            lane_cmncal_done_out,
output wire            lane_disable_out,

// CREG bus
input  wire [15:0]     cr_wr_data,
input  wire            cr_wr_en,
input  wire [31:0]     cr_lane_aon_sel,
input  wire [31:0]     cr_lane_aon_sel2,
output wire [15:0]     cr_lane_aon_rd_data,

// Scan signals
input  wire        scan_mode,              
input  wire        scan_set_rst
);

// Zero ack's during isolation
//assign tx_ack = tx_ack_int & ~isolate_en;
//assign rx_ack = rx_ack_int & ~isolate_en;
// Mantis 6768 - hand-instantiated logic for tx_ack and rx_ack
dwc_e12mp_phy_x4_ns_gen_clk_and2 tx_ack_and (
  .out (tx_ack), 
  .clk (tx_ack_int), 
  .en  (~isolate_en)
);
dwc_e12mp_phy_x4_ns_gen_clk_and2 rx_ack_and (
  .out (rx_ack), 
  .clk (rx_ack_int), 
  .en  (~isolate_en)
);

// IDAC Offset Registers
wire [7:0]  att_idac_ofst_r;
wire [7:0]  ctle_idac_ofst_r;
wire [7:0]  vga1_idac_ofst_r;
wire [7:0]  dfe_sume_idac_ofst_r;
wire [7:0]  dfe_sumo_idac_ofst_r;

// VDAC Offset Registers (Phase)
wire [7:0]  phase_even_vdac_ofst_r;
wire [7:0]  phase_odd_vdac_ofst_r;
wire [7:0]  phase_even_low_vdac_ofst_r;
wire [7:0]  phase_odd_low_vdac_ofst_r;

// VDAC Offset Registers (DFE)
wire [7:0]  dfe_t1eh_vdac_ofst_r;
wire [7:0]  dfe_t1el_vdac_ofst_r;
wire [7:0]  dfe_t1oh_vdac_ofst_r;
wire [7:0]  dfe_t1ol_vdac_ofst_r;
wire [7:0]  dfe_bype_vdac_ofst_r;
wire [7:0]  dfe_bypo_vdac_ofst_r;
wire [7:0]  dfe_erre_vdac_ofst_r;
wire [7:0]  dfe_erro_vdac_ofst_r;

wire [6:0]  rx_iq_phase_adjust_r;

// %%CREG AFE_ATT_IDAC_OFST - Offset value for RX AFE ATT iDAC
//   OFFSET: 0x0
//   ATTR:   RW, CUST
//   FIELDS:
//    [7:0] AFE_ATT_IDAC_OFST  - Offset value for AFE ATT iDAC
//          RESET: 0x80
wire        cr_sel_afe_att_idac_ofst = cr_lane_aon_sel[0];
wire [15:0] cr_afe_att_idac_ofst_rd_data;
dwc_e12mp_phy_x4_ns_cr_rw_reg #(.WIDTH(8), .RST_VAL(8'h80), .MSK_VAL(8'd0))
  afe_att_idac_ofst_reg (
    .cr_val({
             att_idac_ofst_r
             }),
    .cr_rd_data(cr_afe_att_idac_ofst_rd_data),
    .cr_wr_data(cr_wr_data),
    .cr_wr_en(cr_wr_en),
    .cr_clk(cr_clk),
    .cr_rst(cr_rst_aon),
    .cr_sel(cr_sel_afe_att_idac_ofst),
    .cr_self_clr(1'b0)
);

// %%CREG AFE_CTLE_IDAC_OFST - Offset value for RX AFE CTLE iDAC
//   OFFSET: 0x1
//   ATTR:   RW, CUST
//   FIELDS:
//    [7:0] AFE_CTLE_IDAC_OFST  - Offset value for AFE CTLE iDAC
//          RESET: 0x80
wire        cr_sel_afe_ctle_idac_ofst = cr_lane_aon_sel[1];
wire [15:0] cr_afe_ctle_idac_ofst_rd_data;
dwc_e12mp_phy_x4_ns_cr_rw_reg #(.WIDTH(8), .RST_VAL(8'h80), .MSK_VAL(8'd0))
  afe_ctle_idac_ofst_reg (
    .cr_val({
             ctle_idac_ofst_r
             }),
    .cr_rd_data(cr_afe_ctle_idac_ofst_rd_data),
    .cr_wr_data(cr_wr_data),
    .cr_wr_en(cr_wr_en),
    .cr_clk(cr_clk),
    .cr_rst(cr_rst_aon),
    .cr_sel(cr_sel_afe_ctle_idac_ofst),
    .cr_self_clr(1'b0)
);

// %%CREG AFE_VGA1_IDAC_OFST - Offset values for RX AFE VGA1 iDAC
//   OFFSET: 0x2
//   ATTR:   RW, CUST
//   FIELDS:
//    [7:0] AFE_VGA1_IDAC_OFST  - Offset value for AFE VGA1 iDAC
//          RESET: 0x80
wire        cr_sel_afe_vga1_idac_ofst = cr_lane_aon_sel[2];
wire [15:0] cr_afe_vga1_idac_ofst_rd_data;
dwc_e12mp_phy_x4_ns_cr_rw_reg #(.WIDTH(8), .RST_VAL(8'h80), .MSK_VAL(8'd0))
  afe_vga1_idac_ofst_reg (
    .cr_val({
             vga1_idac_ofst_r
             }),
    .cr_rd_data(cr_afe_vga1_idac_ofst_rd_data),
    .cr_wr_data(cr_wr_data),
    .cr_wr_en(cr_wr_en),
    .cr_clk(cr_clk),
    .cr_rst(cr_rst_aon),
    .cr_sel(cr_sel_afe_vga1_idac_ofst),
    .cr_self_clr(1'b0)
);

// %%CREG DFE_SUMMER_EVEN_IDAC_OFST - Offset values for RX DFE Summer Even iDAC
//   OFFSET: 0x3
//   ATTR:   RW, CUST
//   FIELDS:
//    [7:0] DFE_SUMMER_EVEN_IDAC_OFST  - Offset value for DFE Summer Even iDAC
//          RESET: 0x80
wire        cr_sel_dfe_sume_idac_ofst = cr_lane_aon_sel[3];
wire [15:0] cr_dfe_sume_idac_ofst_rd_data;
dwc_e12mp_phy_x4_ns_cr_rw_reg #(.WIDTH(8), .RST_VAL(8'h80), .MSK_VAL(8'd0))
  dfe_sume_idac_ofst_reg (
    .cr_val({
             dfe_sume_idac_ofst_r
             }),
    .cr_rd_data(cr_dfe_sume_idac_ofst_rd_data),
    .cr_wr_data(cr_wr_data),
    .cr_wr_en(cr_wr_en),
    .cr_clk(cr_clk),
    .cr_rst(cr_rst_aon),
    .cr_sel(cr_sel_dfe_sume_idac_ofst),
    .cr_self_clr(1'b0)
);

// %%CREG DFE_SUMMER_ODD_IDAC_OFST - Offset values for RX DFE Summer Odd iDAC
//   OFFSET: 0x4
//   ATTR:   RW, CUST
//   FIELDS:
//    [7:0] DFE_SUMMER_ODD_IDAC_OFST  - Offset value for DFE Summer Odd iDAC
//          RESET: 0x80
wire        cr_sel_dfe_sumo_idac_ofst = cr_lane_aon_sel[4];
wire [15:0] cr_dfe_sumo_idac_ofst_rd_data;
dwc_e12mp_phy_x4_ns_cr_rw_reg #(.WIDTH(8), .RST_VAL(8'h80), .MSK_VAL(8'd0))
  dfe_sumo_idac_ofst_reg (
    .cr_val({
             dfe_sumo_idac_ofst_r
             }),
    .cr_rd_data(cr_dfe_sumo_idac_ofst_rd_data),
    .cr_wr_data(cr_wr_data),
    .cr_wr_en(cr_wr_en),
    .cr_clk(cr_clk),
    .cr_rst(cr_rst_aon),
    .cr_sel(cr_sel_dfe_sumo_idac_ofst),
    .cr_self_clr(1'b0)
);

// %%CREG DFE_PHASE_EVEN_VDAC_OFST - Offset values for RX DFE Phase Even vDAC
//   OFFSET: 0x5
//   ATTR:   RW, CUST
//   FIELDS:
//    [7:0] DFE_PHASE_EVEN_VDAC_OFST  - Offset value for DFE Phase Even vDAC
//          RESET: 0x80
wire        cr_sel_phase_even_vdac_ofst = cr_lane_aon_sel[5];
wire [15:0] cr_phase_even_vdac_ofst_rd_data;
dwc_e12mp_phy_x4_ns_cr_rw_reg #(.WIDTH(8), .RST_VAL(8'h80), .MSK_VAL(8'd0))
  phase_even_vdac_ofst_reg (
    .cr_val({
             phase_even_vdac_ofst_r
             }),
    .cr_rd_data(cr_phase_even_vdac_ofst_rd_data),
    .cr_wr_data(cr_wr_data),
    .cr_wr_en(cr_wr_en),
    .cr_clk(cr_clk),
    .cr_rst(cr_rst_aon),
    .cr_sel(cr_sel_phase_even_vdac_ofst),
    .cr_self_clr(1'b0)
);

// %%CREG DFE_PHASE_ODD_VDAC_OFST - Offset values for RX DFE Phase Odd vDAC
//   OFFSET: 0x6
//   ATTR:   RW, CUST
//   FIELDS:
//    [7:0] DFE_PHASE_ODD_VDAC_OFST  - Offset value for DFE Phase Odd vDAC
//          RESET: 0x80
wire        cr_sel_phase_odd_vdac_ofst = cr_lane_aon_sel[6];
wire [15:0] cr_phase_odd_vdac_ofst_rd_data;
dwc_e12mp_phy_x4_ns_cr_rw_reg #(.WIDTH(8), .RST_VAL(8'h80), .MSK_VAL(8'd0))
  phase_odd_vdac_ofst_reg (
    .cr_val({
             phase_odd_vdac_ofst_r
             }),
    .cr_rd_data(cr_phase_odd_vdac_ofst_rd_data),
    .cr_wr_data(cr_wr_data),
    .cr_wr_en(cr_wr_en),
    .cr_clk(cr_clk),
    .cr_rst(cr_rst_aon),
    .cr_sel(cr_sel_phase_odd_vdac_ofst),
    .cr_self_clr(1'b0)
);

// %%CREG DFE_PHASE_EVEN_LOW_VDAC_OFST - Offset values for RX DFE Phase Even Low vDAC
//   OFFSET: 0x7
//   ATTR:   RW, CUST
//   FIELDS:
//    [7:0] DFE_PHASE_EVEN_LOW_VDAC_OFST  - Offset value for DFE Phase Even Low vDAC
//          RESET: 0x80
wire        cr_sel_phase_even_low_vdac_ofst = cr_lane_aon_sel[7];
wire [15:0] cr_phase_even_low_vdac_ofst_rd_data;
dwc_e12mp_phy_x4_ns_cr_rw_reg #(.WIDTH(8), .RST_VAL(8'h80), .MSK_VAL(8'd0))
  phase_even_low_vdac_ofst_reg (
    .cr_val({
             phase_even_low_vdac_ofst_r
             }),
    .cr_rd_data(cr_phase_even_low_vdac_ofst_rd_data),
    .cr_wr_data(cr_wr_data),
    .cr_wr_en(cr_wr_en),
    .cr_clk(cr_clk),
    .cr_rst(cr_rst_aon),
    .cr_sel(cr_sel_phase_even_low_vdac_ofst),
    .cr_self_clr(1'b0)
);

// %%CREG DFE_PHASE_ODD_LOW_VDAC_OFST - Offset values for RX DFE Phase Odd Low vDAC
//   OFFSET: 0x8
//   ATTR:   RW, CUST
//   FIELDS:
//    [7:0] DFE_PHASE_ODD_LOW_VDAC_OFST  - Offset value for DFE Phase Odd Low vDAC
//          RESET: 0x80
wire        cr_sel_phase_odd_low_vdac_ofst = cr_lane_aon_sel[8];
wire [15:0] cr_phase_odd_low_vdac_ofst_rd_data;
dwc_e12mp_phy_x4_ns_cr_rw_reg #(.WIDTH(8), .RST_VAL(8'h80), .MSK_VAL(8'd0))
  phase_odd_low_vdac_ofst_reg (
    .cr_val({
             phase_odd_low_vdac_ofst_r
             }),
    .cr_rd_data(cr_phase_odd_low_vdac_ofst_rd_data),
    .cr_wr_data(cr_wr_data),
    .cr_wr_en(cr_wr_en),
    .cr_clk(cr_clk),
    .cr_rst(cr_rst_aon),
    .cr_sel(cr_sel_phase_odd_low_vdac_ofst),
    .cr_self_clr(1'b0)
);

// %%CREG RX_PHSADJ_LIN - RX Phase Adjust Linear Value
//   OFFSET: 0x9
//   ATTR:   RW, CUST
//   FIELDS:
//    [4:0] RX_PHSADJ_LIN  - Linear value for RX phase adjust
//          RESET: 0x0
wire        cr_sel_rx_phsadj_lin = cr_lane_aon_sel[9];
wire [4:0]  rx_phsadj_lin_r;
wire [15:0] cr_rx_phsadj_lin_rd_data;
dwc_e12mp_phy_x4_ns_cr_rw_reg #(.WIDTH(5), .RST_VAL(5'h00), .MSK_VAL(5'd0))
  rx_phsadj_lin_reg (
    .cr_val({
             rx_phsadj_lin_r
             }),
    .cr_rd_data(cr_rx_phsadj_lin_rd_data),
    .cr_wr_data(cr_wr_data),
    .cr_wr_en(cr_wr_en),
    .cr_clk(cr_clk),
    .cr_rst(cr_rst_aon),
    .cr_sel(cr_sel_rx_phsadj_lin),
    .cr_self_clr(1'b0)
);

// Perform phase adjust mapping:
// Invert bits [2:0] if linear value is in [8,15]
// (note: max phase adjust value is 23)
wire [4:0] rx_phsadj_map;
assign rx_phsadj_map[4:3] = rx_phsadj_lin_r[4:3];
assign rx_phsadj_map[2:0] = rx_phsadj_lin_r[3] ? ~rx_phsadj_lin_r[2:0] : rx_phsadj_lin_r[2:0];

// %%CREG RX_PHSADJ_MAP - RX Phase Adjust Mapped Value
//   OFFSET: 0xA
//   ATTR: READ, VOL
//   FIELDS:
//     [4:0] RX_PHSADJ_MAP  - Mapped value for RX phase adjust
//
wire        cr_sel_rx_phsadj_map = cr_lane_aon_sel[10];
wire [15:0] cr_rx_phsadj_map_rd_data;
dwc_e12mp_phy_x4_ns_cr_r_reg #(.WIDTH(5)) rx_phsadj_map_reg (
  .cr_rd_data (cr_rx_phsadj_map_rd_data),
  .cr_sel     (cr_sel_rx_phsadj_map),
  .cr_val     ({
                rx_phsadj_map
                })
);

// %%CREG DFE_DATA_EVEN_HIGH_VDAC_OFST - Offset values for RX DFE Data Even High vDAC
//   OFFSET: 0xB
//   ATTR:   RW, CUST
//   FIELDS:
//    [7:0] DFE_DATA_EVEN_HIGH_VDAC_OFST  - Offset value for DFE Data Even High vDAC
//          RESET: 0x80
wire        cr_sel_dfe_t1eh_vdac_ofst = cr_lane_aon_sel[11];
wire [15:0] cr_dfe_t1eh_vdac_ofst_rd_data;
dwc_e12mp_phy_x4_ns_cr_rw_reg #(.WIDTH(8), .RST_VAL(8'h80), .MSK_VAL(8'd0))
  dfe_t1eh_vdac_ofst_reg (
    .cr_val({
             dfe_t1eh_vdac_ofst_r
             }),
    .cr_rd_data(cr_dfe_t1eh_vdac_ofst_rd_data),
    .cr_wr_data(cr_wr_data),
    .cr_wr_en(cr_wr_en),
    .cr_clk(cr_clk),
    .cr_rst(cr_rst_aon),
    .cr_sel(cr_sel_dfe_t1eh_vdac_ofst),
    .cr_self_clr(1'b0)
);

// %%CREG DFE_DATA_EVEN_LOW_VDAC_OFST - Offset values for RX DFE Data Even Low vDAC
//   OFFSET: 0xC
//   ATTR:   RW, CUST
//   FIELDS:
//    [7:0] DFE_DATA_EVEN_LOW_VDAC_OFST  - Offset value for DFE Data Even Low vDAC
//          RESET: 0x80
wire        cr_sel_dfe_t1el_vdac_ofst = cr_lane_aon_sel[12];
wire [15:0] cr_dfe_t1el_vdac_ofst_rd_data;
dwc_e12mp_phy_x4_ns_cr_rw_reg #(.WIDTH(8), .RST_VAL(8'h80), .MSK_VAL(8'd0))
  dfe_t1el_vdac_ofst_reg (
    .cr_val({
             dfe_t1el_vdac_ofst_r
             }),
    .cr_rd_data(cr_dfe_t1el_vdac_ofst_rd_data),
    .cr_wr_data(cr_wr_data),
    .cr_wr_en(cr_wr_en),
    .cr_clk(cr_clk),
    .cr_rst(cr_rst_aon),
    .cr_sel(cr_sel_dfe_t1el_vdac_ofst),
    .cr_self_clr(1'b0)
);

// %%CREG DFE_DATA_ODD_HIGH_VDAC_OFST - Offset values for RX DFE Data Odd High vDAC
//   OFFSET: 0xD
//   ATTR:   RW, CUST
//   FIELDS:
//    [7:0] DFE_DATA_ODD_HIGH_VDAC_OFST  - Offset value for DFE Data Odd High vDAC
//          RESET: 0x80
wire        cr_sel_dfe_t1oh_vdac_ofst = cr_lane_aon_sel[13];
wire [15:0] cr_dfe_t1oh_vdac_ofst_rd_data;
dwc_e12mp_phy_x4_ns_cr_rw_reg #(.WIDTH(8), .RST_VAL(8'h80), .MSK_VAL(8'd0))
  dfe_t1oh_vdac_ofst_reg (
    .cr_val({
             dfe_t1oh_vdac_ofst_r
             }),
    .cr_rd_data(cr_dfe_t1oh_vdac_ofst_rd_data),
    .cr_wr_data(cr_wr_data),
    .cr_wr_en(cr_wr_en),
    .cr_clk(cr_clk),
    .cr_rst(cr_rst_aon),
    .cr_sel(cr_sel_dfe_t1oh_vdac_ofst),
    .cr_self_clr(1'b0)
);

// %%CREG DFE_DATA_ODD_LOW_VDAC_OFST - Offset values for RX DFE Data Odd Low vDAC
//   OFFSET: 0xE
//   ATTR:   RW, CUST
//   FIELDS:
//    [7:0] DFE_DATA_ODD_LOW_VDAC_OFST  - Offset value for DFE Data Odd Low vDAC
//          RESET: 0x80
wire        cr_sel_dfe_t1ol_vdac_ofst = cr_lane_aon_sel[14];
wire [15:0] cr_dfe_t1ol_vdac_ofst_rd_data;
dwc_e12mp_phy_x4_ns_cr_rw_reg #(.WIDTH(8), .RST_VAL(8'h80), .MSK_VAL(8'd0))
  dfe_t1ol_vdac_ofst_reg (
    .cr_val({
             dfe_t1ol_vdac_ofst_r
             }),
    .cr_rd_data(cr_dfe_t1ol_vdac_ofst_rd_data),
    .cr_wr_data(cr_wr_data),
    .cr_wr_en(cr_wr_en),
    .cr_clk(cr_clk),
    .cr_rst(cr_rst_aon),
    .cr_sel(cr_sel_dfe_t1ol_vdac_ofst),
    .cr_self_clr(1'b0)
);

// %%CREG DFE_BYPASS_EVEN_VDAC_OFST - Offset values for RX DFE By-Pass Even vDAC
//   OFFSET: 0x0F
//   ATTR:   RW, CUST
//   FIELDS:
//    [7:0] DFE_BYPASS_EVEN_VDAC_OFST  - Offset value for DFE By-Pass Even vDAC
//          RESET: 0x80
wire        cr_sel_dfe_bype_vdac_ofst = cr_lane_aon_sel[15];
wire [15:0] cr_dfe_bype_vdac_ofst_rd_data;
dwc_e12mp_phy_x4_ns_cr_rw_reg #(.WIDTH(8), .RST_VAL(8'h80), .MSK_VAL(8'd0))
  dfe_bype_vdac_ofst_reg (
    .cr_val({
             dfe_bype_vdac_ofst_r
             }),
    .cr_rd_data(cr_dfe_bype_vdac_ofst_rd_data),
    .cr_wr_data(cr_wr_data),
    .cr_wr_en(cr_wr_en),
    .cr_clk(cr_clk),
    .cr_rst(cr_rst_aon),
    .cr_sel(cr_sel_dfe_bype_vdac_ofst),
    .cr_self_clr(1'b0)
);

// %%CREG DFE_BYPASS_ODD_VDAC_OFST - Offset values for RX DFE By-Pass Odd vDAC
//   OFFSET: 0x10
//   ATTR:   RW, CUST
//   FIELDS:
//    [7:0] DFE_BYPASS_ODD_VDAC_OFST  - Offset value for DFE By-Pass Odd vDAC
//          RESET: 0x80
wire        cr_sel_dfe_bypo_vdac_ofst = cr_lane_aon_sel[16];
wire [15:0] cr_dfe_bypo_vdac_ofst_rd_data;
dwc_e12mp_phy_x4_ns_cr_rw_reg #(.WIDTH(8), .RST_VAL(8'h80), .MSK_VAL(8'd0))
  dfe_bypo_vdac_ofst_reg (
    .cr_val({
             dfe_bypo_vdac_ofst_r
             }),
    .cr_rd_data(cr_dfe_bypo_vdac_ofst_rd_data),
    .cr_wr_data(cr_wr_data),
    .cr_wr_en(cr_wr_en),
    .cr_clk(cr_clk),
    .cr_rst(cr_rst_aon),
    .cr_sel(cr_sel_dfe_bypo_vdac_ofst),
    .cr_self_clr(1'b0)
);

// %%CREG DFE_ERROR_EVEN_VDAC_OFST - Offset values for RX DFE Error Even vDAC
//   OFFSET: 0x11
//   ATTR:   RW, CUST
//   FIELDS:
//    [7:0] DFE_ERROR_EVEN_VDAC_OFST  - Offset value for DFE Error Even vDAC
//          RESET: 0x80
wire        cr_sel_dfe_erre_vdac_ofst = cr_lane_aon_sel[17];
wire [15:0] cr_dfe_erre_vdac_ofst_rd_data;
dwc_e12mp_phy_x4_ns_cr_rw_reg #(.WIDTH(8), .RST_VAL(8'h80), .MSK_VAL(8'd0))
  dfe_erre_vdac_ofst_reg (
    .cr_val({
             dfe_erre_vdac_ofst_r
             }),
    .cr_rd_data(cr_dfe_erre_vdac_ofst_rd_data),
    .cr_wr_data(cr_wr_data),
    .cr_wr_en(cr_wr_en),
    .cr_clk(cr_clk),
    .cr_rst(cr_rst_aon),
    .cr_sel(cr_sel_dfe_erre_vdac_ofst),
    .cr_self_clr(1'b0)
);

// %%CREG DFE_ERROR_ODD_VDAC_OFST - Offset values for RX DFE Error Odd vDAC
//   OFFSET: 0x12
//   ATTR:   RW, CUST
//   FIELDS:
//    [7:0] DFE_ERROR_ODD_VDAC_OFST  - Offset value for DFE Error Odd vDAC
//          RESET: 0x80
wire        cr_sel_dfe_erro_vdac_ofst = cr_lane_aon_sel[18];
wire [15:0] cr_dfe_erro_vdac_ofst_rd_data;
dwc_e12mp_phy_x4_ns_cr_rw_reg #(.WIDTH(8), .RST_VAL(8'h80), .MSK_VAL(8'd0))
  dfe_erro_vdac_ofst_reg (
    .cr_val({
             dfe_erro_vdac_ofst_r
             }),
    .cr_rd_data(cr_dfe_erro_vdac_ofst_rd_data),
    .cr_wr_data(cr_wr_data),
    .cr_wr_en(cr_wr_en),
    .cr_clk(cr_clk),
    .cr_rst(cr_rst_aon),
    .cr_sel(cr_sel_dfe_erro_vdac_ofst),
    .cr_self_clr(1'b0)
);

// %%CREG RX_IQ_PHASE_ADJUST - Value for RX IQ PHASE Adjust
//   OFFSET: 0x13
//   ATTR:   RW, CUST
//   FIELDS:
//    [6:0] RX_IQ_PHASE_ADJUST  - Value for RX IQ PHASE Adjust
//          RESET: 0x07
wire        cr_sel_rx_iq_phase_adjust = cr_lane_aon_sel[19];
wire [15:0] cr_rx_iq_phase_adjust_rd_data;
dwc_e12mp_phy_x4_ns_cr_rw_reg #(.WIDTH(7), .RST_VAL(7'b0000111), .MSK_VAL(7'd0))
  rx_iq_phase_adjust_reg (
    .cr_val({
             rx_iq_phase_adjust_r[6:0]
             }),
    .cr_rd_data(cr_rx_iq_phase_adjust_rd_data),
    .cr_wr_data(cr_wr_data),
    .cr_wr_en(cr_wr_en),
    .cr_clk(cr_clk),
    .cr_rst(cr_rst_aon),
    .cr_sel(cr_sel_rx_iq_phase_adjust),
    .cr_self_clr(1'b0)
);

// %%CREG MPLLA_COARSE_TUNE - MPLLA_COARSE_TUNE
//   OFFSET: 0x14
//   ATTR:   RW, CUST
//   FIELDS:
//     [7:0] MPLLA_COARSE_TUNE - Stored coarse tune value for MPLLA
//          RESET: 0x0
wire        cr_sel_mplla_coarse_tune = cr_lane_aon_sel[20];
wire [7:0]  mplla_coarse_tune_r;
wire [15:0] cr_mplla_coarse_tune_rd_data;
dwc_e12mp_phy_x4_ns_cr_rw_reg #(.WIDTH(8), .RST_VAL(8'h00), .MSK_VAL(8'd0))
  mplla_coarse_tune_reg (
    .cr_val({
             mplla_coarse_tune_r
             }),
    .cr_rd_data(cr_mplla_coarse_tune_rd_data),
    .cr_wr_data(cr_wr_data),
    .cr_wr_en(cr_wr_en),
    .cr_clk(cr_clk),
    .cr_rst(cr_rst_aon),
    .cr_sel(cr_sel_mplla_coarse_tune),
    .cr_self_clr(1'b0)
);

// %%CREG MPLLB_COARSE_TUNE - MPLLB_COARSE_TUNE
//   OFFSET: 0x15
//   ATTR:   RW, CUST
//   FIELDS:
//     [7:0] MPLLB_COARSE_TUNE - Stored coarse tune value for MPLLB
//           RESET: 0x0
wire        cr_sel_mpllb_coarse_tune = cr_lane_aon_sel[21];
wire [7:0]  mpllb_coarse_tune_r;
wire [15:0] cr_mpllb_coarse_tune_rd_data;
dwc_e12mp_phy_x4_ns_cr_rw_reg #(.WIDTH(8), .RST_VAL(8'h00), .MSK_VAL(8'd0))
  mpllb_coarse_tune_reg (
    .cr_val({
             mpllb_coarse_tune_r
             }),
    .cr_rd_data(cr_mpllb_coarse_tune_rd_data),
    .cr_wr_data(cr_wr_data),
    .cr_wr_en(cr_wr_en),
    .cr_clk(cr_clk),
    .cr_rst(cr_rst_aon),
    .cr_sel(cr_sel_mpllb_coarse_tune),
    .cr_self_clr(1'b0)
);

// %%CREG RTUNE_RX_VAL - Resistor Tune RX Value
//   OFFSET: 0x16
//   ATTR:   RW, CUST
//   FIELDS:
//     [5:0] RTUNE_RX_VAL - Stored resister tune RX value
//           RESET: 0x0
wire        cr_sel_rtune_rx_val = cr_lane_aon_sel[22];
wire [5:0]  rtune_rx_val_r;
wire [15:0] cr_rtune_rx_val_rd_data;
dwc_e12mp_phy_x4_ns_cr_rw_reg #(.WIDTH(6), .RST_VAL(6'h00), .MSK_VAL(6'd0))
  rtune_rx_val_reg (
    .cr_val({
             rtune_rx_val_r
             }),
    .cr_rd_data(cr_rtune_rx_val_rd_data),
    .cr_wr_data(cr_wr_data),
    .cr_wr_en(cr_wr_en),
    .cr_clk(cr_clk),
    .cr_rst(cr_rst_aon),
    .cr_sel(cr_sel_rtune_rx_val),
    .cr_self_clr(1'b0)
);

// %%CREG RTUNE_TXDN_VAL - Resistor Tune TX Down Value
//   OFFSET: 0x17
//   ATTR:   RW, CUST
//   FIELDS:
//     [9:0] RTUNE_TXDN_VAL - Stored resister tune TX down value
//           RESET: 0x0
wire        cr_sel_rtune_txdn_val = cr_lane_aon_sel[23];
wire [9:0]  rtune_txdn_val_r;
wire [15:0] cr_rtune_txdn_val_rd_data;
dwc_e12mp_phy_x4_ns_cr_rw_reg #(.WIDTH(10), .RST_VAL(10'h00), .MSK_VAL(10'd0))
  rtune_txdn_val_reg (
    .cr_val({
             rtune_txdn_val_r
             }),
    .cr_rd_data(cr_rtune_txdn_val_rd_data),
    .cr_wr_data(cr_wr_data),
    .cr_wr_en(cr_wr_en),
    .cr_clk(cr_clk),
    .cr_rst(cr_rst_aon),
    .cr_sel(cr_sel_rtune_txdn_val),
    .cr_self_clr(1'b0)
);

// %%CREG RTUNE_TXUP_VAL - Resistor Tune TX Up Value
//   OFFSET: 0x18
//   ATTR:   RW, CUST
//   FIELDS:
//     [9:0] RTUNE_TXUP_VAL - Stored resister tune TX up value
//           RESET: 0x0
wire        cr_sel_rtune_txup_val = cr_lane_aon_sel[24];
wire [9:0]  rtune_txup_val_r;
wire [15:0] cr_rtune_txup_val_rd_data;
dwc_e12mp_phy_x4_ns_cr_rw_reg #(.WIDTH(10), .RST_VAL(10'h00), .MSK_VAL(10'd0))
  rtune_txup_val_reg (
    .cr_val({
             rtune_txup_val_r
             }),
    .cr_rd_data(cr_rtune_txup_val_rd_data),
    .cr_wr_data(cr_wr_data),
    .cr_wr_en(cr_wr_en),
    .cr_clk(cr_clk),
    .cr_rst(cr_rst_aon),
    .cr_sel(cr_sel_rtune_txup_val),
    .cr_self_clr(1'b0)
);

// %%CREG INIT_PWRUP_DONE - Initial Power-Up Done Status
//   OFFSET: 0x19
//   ATTR:   RW, CUST
//   FIELDS:
//       [0] INIT_PWRUP_DONE - Indicates whether initial power-up has completed or not.
//           RESET: 0x0
wire        cr_sel_init_pwrup_done = cr_lane_aon_sel[25];
wire [15:0] cr_init_pwrup_done_rd_data;
dwc_e12mp_phy_x4_ns_cr_rw_reg #(.WIDTH(1), .RST_VAL(1'h0), .MSK_VAL(1'd0))
  init_pwrup_done_reg (
    .cr_val({
             lane_init_pwrup_done_r
             }),
    .cr_rd_data(cr_init_pwrup_done_rd_data),
    .cr_wr_data(cr_wr_data),
    .cr_wr_en(cr_wr_en),
    .cr_clk(cr_clk),
    .cr_rst(cr_rst_aon),
    .cr_sel(cr_sel_init_pwrup_done),
    .cr_self_clr(1'b0)
);

// %%CREG RX_ADPT_ATT - RX Adapted value of ATT
//   OFFSET: 0x1A
//   ATTR:   RW, CUST
//   FIELDS:
//     [7:0] ATT_ADPT_VAL - Stored RX adapted ATT value
//           RESET: 0x0
wire        cr_sel_rx_att_adpt_val = cr_lane_aon_sel[26];
wire [15:0] cr_rx_att_adpt_val_rd_data;
dwc_e12mp_phy_x4_ns_cr_rw_reg #(.WIDTH(8), .RST_VAL(8'h00), .MSK_VAL(8'd0))
  rx_att_adpt_val_reg (
    .cr_val({
             rx_att_adpt_val_r
             }),
    .cr_rd_data(cr_rx_att_adpt_val_rd_data),
    .cr_wr_data(cr_wr_data),
    .cr_wr_en(cr_wr_en),
    .cr_clk(cr_clk),
    .cr_rst(cr_rst_aon),
    .cr_sel(cr_sel_rx_att_adpt_val),
    .cr_self_clr(1'b0)
);

// %%CREG RX_ADPT_VGA - RX Adapted value of VGA
//   OFFSET: 0x1B
//   ATTR:   RW, CUST
//   FIELDS:
//     [9:0] VGA_ADPT_VAL - Stored RX adapted VGA value
//           RESET: 0x0
wire        cr_sel_rx_vga_adpt_val = cr_lane_aon_sel[27];
wire [15:0] cr_rx_vga_adpt_val_rd_data;
dwc_e12mp_phy_x4_ns_cr_rw_reg #(.WIDTH(10), .RST_VAL(10'h000), .MSK_VAL(10'd0))
  rx_vga_adpt_val_reg (
    .cr_val({
             rx_vga_adpt_val_r
             }),
    .cr_rd_data(cr_rx_vga_adpt_val_rd_data),
    .cr_wr_data(cr_wr_data),
    .cr_wr_en(cr_wr_en),
    .cr_clk(cr_clk),
    .cr_rst(cr_rst_aon),
    .cr_sel(cr_sel_rx_vga_adpt_val),
    .cr_self_clr(1'b0)
);

// %%CREG RX_ADPT_CTLE - RX Adapted value of CTLE
//   OFFSET: 0x1C
//   ATTR:   RW, CUST
//   FIELDS:
//   [12:10] CTLE_POLE_ADPT_VAL - Stored RX adapted CTLE pole value
//           RESET: 0x0
//     [9:0] CTLE_BOOST_ADPT_VAL - Stored RX adapted CTLE boost value
//           RESET: 0x0
wire        cr_sel_rx_ctle_adpt_val = cr_lane_aon_sel[28];
wire [15:0] cr_rx_ctle_adpt_val_rd_data;
dwc_e12mp_phy_x4_ns_cr_rw_reg #(.WIDTH(13), .RST_VAL(13'h0000), .MSK_VAL(13'd0))
  rx_ctle_adpt_val_reg (
    .cr_val({
             rx_ctle_pole_adpt_val_r,
             rx_ctle_boost_adpt_val_r
             }),
    .cr_rd_data(cr_rx_ctle_adpt_val_rd_data),
    .cr_wr_data(cr_wr_data),
    .cr_wr_en(cr_wr_en),
    .cr_clk(cr_clk),
    .cr_rst(cr_rst_aon),
    .cr_sel(cr_sel_rx_ctle_adpt_val),
    .cr_self_clr(1'b0)
);

// %%CREG RX_ADPT_DFE_TAP1 - RX Adapted value of DFE TAP1
//   OFFSET: 0x1D
//   ATTR:   RW, CUST
//   FIELDS:
//    [12:0] DFE_TAP1_ADPT_VAL - Stored RX adapted DFE TAP1 value
//           RESET: 0x0
wire        cr_sel_rx_dfe_tap1_adpt_val = cr_lane_aon_sel[29];
wire [15:0] cr_rx_dfe_tap1_adpt_val_rd_data;
dwc_e12mp_phy_x4_ns_cr_rw_reg #(.WIDTH(13), .RST_VAL(13'h0000), .MSK_VAL(13'd0))
  rx_dfe_tap1_adpt_val_reg (
    .cr_val({
             rx_dfe_tap1_adpt_val_r
             }),
    .cr_rd_data(cr_rx_dfe_tap1_adpt_val_rd_data),
    .cr_wr_data(cr_wr_data),
    .cr_wr_en(cr_wr_en),
    .cr_clk(cr_clk),
    .cr_rst(cr_rst_aon),
    .cr_sel(cr_sel_rx_dfe_tap1_adpt_val),
    .cr_self_clr(1'b0)
);

// Mantis 6616
// rx_reset should also reset rx_adpt_done_r
// Mantis 6810 - For async resets that already have scan_rst muxed
// onto them, AND them with ~scan_mode to prevent C26 DFT violations
// on the atpg_cov flop within the pcs_raw_gen_rst_sync.
wire cr_rx_rst_aon_async;
dwc_e12mp_phy_x4_ns_gen_clk_and2 cr_rx_rst_aon_scan_and (
  .out (cr_rx_rst_aon_async), 
  .clk (cr_rst_aon | rx_reset), 
  .en  (~scan_mode)
);

wire cr_rx_rst_aon;
dwc_e12mp_phy_x4_ns_pcs_raw_gen_rst_sync #(.ATPG_COV(0)) cr_rx_rst_aon_sync (
  .sync_rst       (cr_rx_rst_aon),
  .clk            (cr_clk),
  .async_rst      (cr_rx_rst_aon_async),
  .scan_mode_i    (scan_mode),
  .scan_set_rst_i (scan_set_rst)
);

// %%CREG RX_ADAPT_DONE - RX Adaptation Done Status
//   OFFSET: 0x1E
//   ATTR:   RW, CUST
//   FIELDS:
//       [0] RX_ADAPT_DONE - Indicates whether RX adaptation has completed or not.
//           RESET: 0x0
wire        cr_sel_rx_adpt_done = cr_lane_aon_sel[30];
wire [15:0] cr_rx_adpt_done_rd_data;
dwc_e12mp_phy_x4_ns_cr_rw_reg #(.WIDTH(1), .RST_VAL(1'b0), .MSK_VAL(1'd0))
  rx_adpt_done_reg (
    .cr_val({
             rx_adpt_done_r
             }),
    .cr_rd_data(cr_rx_adpt_done_rd_data),
    .cr_wr_data(cr_wr_data),
    .cr_wr_en(cr_wr_en),
    .cr_clk(cr_clk),
    .cr_rst(cr_rx_rst_aon),
    .cr_sel(cr_sel_rx_adpt_done),
    .cr_self_clr(1'b0)
);

// %%CREG FAST_FLAGS - Fast flags for simulation only
//   OFFSET: 0x1F
//   ATTR:   RW, CUST
//   FIELDS:
//     [14] FAST_RX_VCO_CAL     - Enable fast RX VCO Calibration
//          RESET: 0x0
//     [13] FAST_RX_VCO_WAIT    - Enable fast RX VCO wait times
//          RESET: 0x0
//     [12] FAST_RX_PWRUP       - Enable fast RX power-up (LOS, VREG/AFE and DCC)
//          RESET: 0x0
//     [11] FAST_TX_RXDET       - Enable fast TX Detect RX
//          RESET: 0x0
//     [10] FAST_TX_CMN_MODE    - Enable fast TX Common Mode Charge-up
//          RESET: 0x0
//      [9] FAST_SUP            - Enable fast Support block (MPLL and Rtune)
//          RESET: 0x0
//      [8] FAST_RX_DFE_ADAPT   - Enables fast RX DFE DAC start-up adaptation
//          RESET: 0x0
//      [7] FAST_RX_AFE_ADAPT   - Enables fast RX AFE DAC start-up adaptation
//          RESET: 0x0
//      [6] FAST_RX_IQ_CAL      - Enables fast RX IQ start-up calibration
//          RESET: 0x0
//      [5] FAST_RX_REFLVL_CAL  - Enables fast RX reference level (100mv, 125mv, 150mv) start-up calibration
//          RESET: 0x0
//      [4] FAST_RX_BYPASS_CAL  - Enables fast RX Bypass slicer start-up calibration
//          RESET: 0x0
//      [3] FAST_RX_DFE_CAL     - Enables fast RX DFE slicer start-up calibration
//          RESET: 0x0
//      [2] FAST_RX_AFE_CAL     - Enables fast RX AFE DAC start-up calibration
//          RESET: 0x0
//      [1] FAST_RX_ADAPT       - Enables fast RX adaptation
//          RESET: 0x0
//      [0] FAST_RX_STARTUP_CAL - Enables fast RX start-up calibration
//          RESET: 0x0
wire        cr_sel_fast_flags = cr_lane_aon_sel[31];
wire [15:0] cr_fast_flags_rd_data;
dwc_e12mp_phy_x4_ns_cr_rw_reg #(.WIDTH(15), .RST_VAL({`FAST_RX_VCO_CAL_INIT_VAL,
                                  `FAST_RX_VCO_WAIT_INIT_VAL,
                                  `FAST_RX_PWRUP_INIT_VAL,
                                  `FAST_TX_RXDET_INIT_VAL,
                                  `FAST_TX_VCM_HOLD_INIT_VAL,
                                  `FAST_SUP_INIT_VAL,        
                                  `FAST_RX_DFE_ADAPT_INIT_VAL,
                                  `FAST_RX_AFE_ADAPT_INIT_VAL,
                                  `FAST_RX_IQ_CAL_INIT_VAL,
                                  `FAST_RX_REFLVL_CAL_INIT_VAL,
                                  `FAST_RX_BYPASS_CAL_INIT_VAL,
                                  `FAST_RX_DFE_CAL_INIT_VAL,
                                  `FAST_RX_AFE_CAL_INIT_VAL,
                                  `FAST_RX_ADAPT_INIT_VAL,
                                  `FAST_RX_STARTUP_CAL_INIT_VAL}),
                                  .MSK_VAL(15'd0))
  fast_flags_reg (
    .cr_val({
             rx_fast_vco_cal_r,
             rx_fast_vco_wait_r,
             rx_fast_pwrup_r,
             tx_fast_rxdet_r,
             tx_fast_cmn_mode_r,
             tx_fast_sup_r,
             rx_fast_dfe_adapt_r,
             rx_fast_afe_adapt_r,
             rx_fast_iq_cal_r,
             rx_fast_reflvl_cal_r,
             rx_fast_bypass_cal_r,
             rx_fast_dfe_cal_r,
             rx_fast_afe_cal_r,
             rx_fast_adapt_r,
             rx_fast_startup_cal_r
             }),
    .cr_rd_data(cr_fast_flags_rd_data),
    .cr_wr_data(cr_wr_data),
    .cr_wr_en(cr_wr_en),
    .cr_clk(cr_clk),
    .cr_rst(cr_rst_aon),
    .cr_sel(cr_sel_fast_flags),
    .cr_self_clr(1'b0)
);

// %%CREG RX_ADPT_DFE_TAP2 - RX Adapted value of DFE TAP2
//   OFFSET: 0x20
//   ATTR:   RW, CUST
//   FIELDS:
//    [11:0] DFE_TAP2_ADPT_VAL - Stored RX adapted DFE TAP2 value
//           RESET: 0x800
wire        cr_sel_rx_dfe_tap2_adpt_val = cr_lane_aon_sel2[0];
wire [15:0] cr_rx_dfe_tap2_adpt_val_rd_data;
dwc_e12mp_phy_x4_ns_cr_rw_reg #(.WIDTH(12), .RST_VAL(12'h800), .MSK_VAL(12'd0))
  rx_dfe_tap2_adpt_val_reg (
    .cr_val({
             rx_dfe_tap2_adpt_val_r
             }),
    .cr_rd_data(cr_rx_dfe_tap2_adpt_val_rd_data),
    .cr_wr_data(cr_wr_data),
    .cr_wr_en(cr_wr_en),
    .cr_clk(cr_clk),
    .cr_rst(cr_rst_aon),
    .cr_sel(cr_sel_rx_dfe_tap2_adpt_val),
    .cr_self_clr(1'b0)
);

// %%CREG RX_ADPT_DFE_TAP3 - RX Adapted value of DFE TAP3
//   OFFSET: 0x21
//   ATTR:   RW, CUST
//   FIELDS:
//    [11:0] DFE_TAP3_ADPT_VAL - Stored RX adapted DFE TAP3 value
//           RESET: 0x800
wire        cr_sel_rx_dfe_tap3_adpt_val = cr_lane_aon_sel2[1];
wire [15:0] cr_rx_dfe_tap3_adpt_val_rd_data;
dwc_e12mp_phy_x4_ns_cr_rw_reg #(.WIDTH(12), .RST_VAL(12'h800), .MSK_VAL(12'd0))
  rx_dfe_tap3_adpt_val_reg (
    .cr_val({
             rx_dfe_tap3_adpt_val_r
             }),
    .cr_rd_data(cr_rx_dfe_tap3_adpt_val_rd_data),
    .cr_wr_data(cr_wr_data),
    .cr_wr_en(cr_wr_en),
    .cr_clk(cr_clk),
    .cr_rst(cr_rst_aon),
    .cr_sel(cr_sel_rx_dfe_tap3_adpt_val),
    .cr_self_clr(1'b0)
);

// %%CREG RX_ADPT_DFE_TAP4 - RX Adapted value of DFE TAP4
//   OFFSET: 0x22
//   ATTR:   RW, CUST
//   FIELDS:
//    [11:0] DFE_TAP4_ADPT_VAL - Stored RX adapted DFE TAP4 value
//           RESET: 0x800
wire        cr_sel_rx_dfe_tap4_adpt_val = cr_lane_aon_sel2[2];
wire [15:0] cr_rx_dfe_tap4_adpt_val_rd_data;
dwc_e12mp_phy_x4_ns_cr_rw_reg #(.WIDTH(12), .RST_VAL(12'h800), .MSK_VAL(12'd0))
  rx_dfe_tap4_adpt_val_reg (
    .cr_val({
             rx_dfe_tap4_adpt_val_r
             }),
    .cr_rd_data(cr_rx_dfe_tap4_adpt_val_rd_data),
    .cr_wr_data(cr_wr_data),
    .cr_wr_en(cr_wr_en),
    .cr_clk(cr_clk),
    .cr_rst(cr_rst_aon),
    .cr_sel(cr_sel_rx_dfe_tap4_adpt_val),
    .cr_self_clr(1'b0)
);

// %%CREG RX_ADPT_DFE_TAP5 - RX Adapted value of DFE TAP5
//   OFFSET: 0x23
//   ATTR:   RW, CUST
//   FIELDS:
//    [11:0] DFE_TAP5_ADPT_VAL - Stored RX adapted DFE TAP5 value
//           RESET: 0x800
wire        cr_sel_rx_dfe_tap5_adpt_val = cr_lane_aon_sel2[3];
wire [15:0] cr_rx_dfe_tap5_adpt_val_rd_data;
dwc_e12mp_phy_x4_ns_cr_rw_reg #(.WIDTH(12), .RST_VAL(12'h800), .MSK_VAL(12'd0))
  rx_dfe_tap5_adpt_val_reg (
    .cr_val({
             rx_dfe_tap5_adpt_val_r
             }),
    .cr_rd_data(cr_rx_dfe_tap5_adpt_val_rd_data),
    .cr_wr_data(cr_wr_data),
    .cr_wr_en(cr_wr_en),
    .cr_clk(cr_clk),
    .cr_rst(cr_rst_aon),
    .cr_sel(cr_sel_rx_dfe_tap5_adpt_val),
    .cr_self_clr(1'b0)
);

// %%CREG RX_SLICER_CTRL_EVEN - Sets values for RX SLICER CTRL EVEN signals going to ANA
//   OFFSET: 0x24
//   ATTR:   RW, CUST
//   FIELDS:
//    [3:0] RX_ANA_SLICER_CTRL_E    - Value for rx_ana_slicer_ctrl_e[3:0]
//          RESET: 0x7
wire  [3:0] rx_ana_slicer_ctrl_e_r;
wire        cr_sel_rx_slicer_ctrl_e = cr_lane_aon_sel2[4];
wire [15:0] cr_rx_slicer_ctrl_e_rd_data;
dwc_e12mp_phy_x4_ns_cr_rw_reg #(.WIDTH(4), .RST_VAL(4'b0111), .MSK_VAL(4'd0))
  rx_slicer_ctrl_e_reg (
    .cr_val({
             rx_ana_slicer_ctrl_e_r
             }),
    .cr_rd_data(cr_rx_slicer_ctrl_e_rd_data),
    .cr_wr_data(cr_wr_data),
    .cr_wr_en(cr_wr_en),
    .cr_clk(cr_clk),
    .cr_rst(cr_rst_aon),
    .cr_sel(cr_sel_rx_slicer_ctrl_e),
    .cr_self_clr(1'b0)
);

// %%CREG RX_SLICER_CTRL_ODD - Sets values for RX SLICER CTRL ODD signals going to ANA
//   OFFSET: 0x25
//   ATTR:   RW, CUST
//   FIELDS:
//    [3:0] RX_ANA_SLICER_CTRL_O    - Value for rx_ana_slicer_ctrl_o[3:0]
//          RESET: 0x7
wire  [3:0] rx_ana_slicer_ctrl_o_r;
wire        cr_sel_rx_slicer_ctrl_o = cr_lane_aon_sel2[5];
wire [15:0] cr_rx_slicer_ctrl_o_rd_data;
dwc_e12mp_phy_x4_ns_cr_rw_reg #(.WIDTH(4), .RST_VAL(4'b0111), .MSK_VAL(4'd0))
  rx_slicer_ctrl_o_reg (
    .cr_val({
             rx_ana_slicer_ctrl_o_r
             }),
    .cr_rd_data(cr_rx_slicer_ctrl_o_rd_data),
    .cr_wr_data(cr_wr_data),
    .cr_wr_en(cr_wr_en),
    .cr_clk(cr_clk),
    .cr_rst(cr_rst_aon),
    .cr_sel(cr_sel_rx_slicer_ctrl_o),
    .cr_self_clr(1'b0)
);

// %%CREG LANE_CMNCAL_STATUS - Common Calibration Status
//   OFFSET: 0x26
//   ATTR:   RW, CUST
//   FIELDS:
//       [1] LANE_CMNCAL_DONE    - Indicates whether common calibration (mpll and rtune)
//           NOTES:                has been completed by this lane or not.
//           RESET: 0x0
//       [0] LANE_CMNCAL_INIT    - Indicates whether common calibration (mpll and rtune)
//           NOTES:                has been started by this lane or not.
//           RESET: 0x0
wire        lane_cmncal_done_r;
wire        lane_cmncal_init_r;
wire        cr_sel_cmncal_sts = cr_lane_aon_sel2[6];
wire [15:0] cr_cmncal_sts_rd_data;
dwc_e12mp_phy_x4_ns_cr_rw_reg #(.WIDTH(2), .RST_VAL(2'b00), .MSK_VAL(2'd0))
  cmncal_sts_reg (
    .cr_val({
             lane_cmncal_done_r,
             lane_cmncal_init_r
             }),
    .cr_rd_data(cr_cmncal_sts_rd_data),
    .cr_wr_data(cr_wr_data),
    .cr_wr_en(cr_wr_en),
    .cr_clk(cr_clk),
    .cr_rst(cr_rst_aon),
    .cr_sel(cr_sel_cmncal_sts),
    .cr_self_clr(1'b0)
);

assign lane_cmncal_init_out = lane_cmncal_init_r | lane_cmncal_init_in;
assign lane_cmncal_done_out = lane_cmncal_done_r | lane_cmncal_done_in;

// %%CREG ADPT_CTL_0 - Adaptation Control register #0
//   OFFSET: 0x27
//   ATTR:   RW, CUST
//   FIELDS:
//    [15:0] VAL    - Value of adaptation control
//           RESET: 0x0
wire [15:0] adpt_ctl_0_r;
wire        cr_sel_adpt_ctl_0 = cr_lane_aon_sel2[7];
wire [15:0] cr_adpt_ctl_0_rd_data;
dwc_e12mp_phy_x4_ns_cr_rw_reg #(.WIDTH(16), .RST_VAL(16'h0000), .MSK_VAL(16'd0))
  adpt_ctl_0_reg (
    .cr_val({
             adpt_ctl_0_r
             }),
    .cr_rd_data(cr_adpt_ctl_0_rd_data),
    .cr_wr_data(cr_wr_data),
    .cr_wr_en(cr_wr_en),
    .cr_clk(cr_clk),
    .cr_rst(cr_rst_aon),
    .cr_sel(cr_sel_adpt_ctl_0),
    .cr_self_clr(1'b0)
);

// %%CREG ADPT_CTL_1 - Adaptation Control register #1
//   OFFSET: 0x28
//   ATTR:   RW, CUST
//   FIELDS:
//    [15:0] VAL    - Value of adaptation control
//           RESET: 0x0
wire [15:0] adpt_ctl_1_r;
wire        cr_sel_adpt_ctl_1 = cr_lane_aon_sel2[8];
wire [15:0] cr_adpt_ctl_1_rd_data;
dwc_e12mp_phy_x4_ns_cr_rw_reg #(.WIDTH(16), .RST_VAL(16'h0000), .MSK_VAL(16'd0))
  adpt_ctl_1_reg (
    .cr_val({
             adpt_ctl_1_r
             }),
    .cr_rd_data(cr_adpt_ctl_1_rd_data),
    .cr_wr_data(cr_wr_data),
    .cr_wr_en(cr_wr_en),
    .cr_clk(cr_clk),
    .cr_rst(cr_rst_aon),
    .cr_sel(cr_sel_adpt_ctl_1),
    .cr_self_clr(1'b0)
);

// %%CREG ADPT_CTL_2 - Adaptation Control register #2
//   OFFSET: 0x29
//   ATTR:   RW, CUST
//   FIELDS:
//    [15:0] VAL    - Value of adaptation control
//           RESET: 0x0
wire [15:0] adpt_ctl_2_r;
wire        cr_sel_adpt_ctl_2 = cr_lane_aon_sel2[9];
wire [15:0] cr_adpt_ctl_2_rd_data;
dwc_e12mp_phy_x4_ns_cr_rw_reg #(.WIDTH(16), .RST_VAL(16'h0000), .MSK_VAL(16'd0))
  adpt_ctl_2_reg (
    .cr_val({
             adpt_ctl_2_r
             }),
    .cr_rd_data(cr_adpt_ctl_2_rd_data),
    .cr_wr_data(cr_wr_data),
    .cr_wr_en(cr_wr_en),
    .cr_clk(cr_clk),
    .cr_rst(cr_rst_aon),
    .cr_sel(cr_sel_adpt_ctl_2),
    .cr_self_clr(1'b0)
);

// %%CREG ADPT_CTL_3 - Adaptation Control register #3
//   OFFSET: 0x2A
//   ATTR:   RW, CUST
//   FIELDS:
//    [15:0] VAL    - Value of adaptation control
//           RESET: 0x0
wire [15:0] adpt_ctl_3_r;
wire        cr_sel_adpt_ctl_3 = cr_lane_aon_sel2[10];
wire [15:0] cr_adpt_ctl_3_rd_data;
dwc_e12mp_phy_x4_ns_cr_rw_reg #(.WIDTH(16), .RST_VAL(16'h0000), .MSK_VAL(16'd0))
  adpt_ctl_3_reg (
    .cr_val({
             adpt_ctl_3_r
             }),
    .cr_rd_data(cr_adpt_ctl_3_rd_data),
    .cr_wr_data(cr_wr_data),
    .cr_wr_en(cr_wr_en),
    .cr_clk(cr_clk),
    .cr_rst(cr_rst_aon),
    .cr_sel(cr_sel_adpt_ctl_3),
    .cr_self_clr(1'b0)
);

// %%CREG ADPT_CTL_4 - Adaptation Control register #4
//   OFFSET: 0x2B
//   ATTR:   RW, CUST
//   FIELDS:
//    [15:0] VAL    - Value of adaptation control
//           RESET: 0x0
wire [15:0] adpt_ctl_4_r;
wire        cr_sel_adpt_ctl_4 = cr_lane_aon_sel2[11];
wire [15:0] cr_adpt_ctl_4_rd_data;
dwc_e12mp_phy_x4_ns_cr_rw_reg #(.WIDTH(16), .RST_VAL(16'h0000), .MSK_VAL(16'd0))
  adpt_ctl_4_reg (
    .cr_val({
             adpt_ctl_4_r
             }),
    .cr_rd_data(cr_adpt_ctl_4_rd_data),
    .cr_wr_data(cr_wr_data),
    .cr_wr_en(cr_wr_en),
    .cr_clk(cr_clk),
    .cr_rst(cr_rst_aon),
    .cr_sel(cr_sel_adpt_ctl_4),
    .cr_self_clr(1'b0)
);

// %%CREG ADPT_CTL_5 - Adaptation Control register #5
//   OFFSET: 0x2C
//   ATTR:   RW, CUST
//   FIELDS:
//    [15:0] VAL    - Value of adaptation control
//           RESET: 0x0
wire [15:0] adpt_ctl_5_r;
wire        cr_sel_adpt_ctl_5 = cr_lane_aon_sel2[12];
wire [15:0] cr_adpt_ctl_5_rd_data;
dwc_e12mp_phy_x4_ns_cr_rw_reg #(.WIDTH(16), .RST_VAL(16'h0000), .MSK_VAL(16'd0))
  adpt_ctl_5_reg (
    .cr_val({
             adpt_ctl_5_r
             }),
    .cr_rd_data(cr_adpt_ctl_5_rd_data),
    .cr_wr_data(cr_wr_data),
    .cr_wr_en(cr_wr_en),
    .cr_clk(cr_clk),
    .cr_rst(cr_rst_aon),
    .cr_sel(cr_sel_adpt_ctl_5),
    .cr_self_clr(1'b0)
);

// %%CREG ADPT_CTL_6 - Adaptation Control register #6
//   OFFSET: 0x2D
//   ATTR:   RW, CUST
//   FIELDS:
//    [15:0] VAL    - Value of adaptation control
//           RESET: 0x0
wire [15:0] adpt_ctl_6_r;
wire        cr_sel_adpt_ctl_6 = cr_lane_aon_sel2[13];
wire [15:0] cr_adpt_ctl_6_rd_data;
dwc_e12mp_phy_x4_ns_cr_rw_reg #(.WIDTH(16), .RST_VAL(16'h0000), .MSK_VAL(16'd0))
  adpt_ctl_6_reg (
    .cr_val({
             adpt_ctl_6_r
             }),
    .cr_rd_data(cr_adpt_ctl_6_rd_data),
    .cr_wr_data(cr_wr_data),
    .cr_wr_en(cr_wr_en),
    .cr_clk(cr_clk),
    .cr_rst(cr_rst_aon),
    .cr_sel(cr_sel_adpt_ctl_6),
    .cr_self_clr(1'b0)
);

// %%CREG ADPT_CTL_7 - Adaptation Control register #7
//   OFFSET: 0x2E
//   ATTR:   RW, CUST
//   FIELDS:
//    [15:0] VAL    - Value of adaptation control
//           RESET: 0x0
wire [15:0] adpt_ctl_7_r;
wire        cr_sel_adpt_ctl_7 = cr_lane_aon_sel2[14];
wire [15:0] cr_adpt_ctl_7_rd_data;
dwc_e12mp_phy_x4_ns_cr_rw_reg #(.WIDTH(16), .RST_VAL(16'h0000), .MSK_VAL(16'd0))
  adpt_ctl_7_reg (
    .cr_val({
             adpt_ctl_7_r
             }),
    .cr_rd_data(cr_adpt_ctl_7_rd_data),
    .cr_wr_data(cr_wr_data),
    .cr_wr_en(cr_wr_en),
    .cr_clk(cr_clk),
    .cr_rst(cr_rst_aon),
    .cr_sel(cr_sel_adpt_ctl_7),
    .cr_self_clr(1'b0)
);

// %%CREG FAST_FLAGS_2 - Fast flags for simulation only
//   OFFSET: 0x2F
//   ATTR:   RW, CUST
//   FIELDS:
//   [11:5] RESERVED            - Reserved
//          RESET: 0x0
//      [4] FAST_RX_CONT_AFE_CAL   - Enables fast RX continuous AFE calibration
//          RESET: 0x0
//      [3] FAST_RX_CONT_PHASE_CAL - Enables fast RX continuous phase calibration
//          RESET: 0x1
//      [2] FAST_RX_CONT_DATA_CAL  - Enables fast RX continuous data calibration
//          RESET: 0x0
//      [1] FAST_RX_CONT_ADAPT     - Enables fast RX continuous adaptation
//          RESET: 0x0
//      [0] FAST_RX_CONT_CAL_ADAPT - Enables fast RX continuous calibration/adaptation
//          RESET: 0x0
wire        cr_sel_fast_flags_2 = cr_lane_aon_sel2[15];
wire [15:0] cr_fast_flags_2_rd_data;
dwc_e12mp_phy_x4_ns_cr_rw_reg #(.WIDTH(12), .RST_VAL({7'd0,
                                  `FAST_RX_CONT_AFE_CAL_INIT_VAL,
                                  `FAST_RX_CONT_PHASE_CAL_INIT_VAL,
                                  `FAST_RX_CONT_DATA_CAL_INIT_VAL,
                                  `FAST_RX_CONT_ADAPT_INIT_VAL,
                                  `FAST_RX_CONT_CAL_ADAPT_INIT_VAL}),
                                  .MSK_VAL(12'd0))
  fast_flags_2_reg (
    .cr_val({
             rx_fast_flags_rsvd_r,
             rx_fast_cont_afe_cal_r,
             rx_fast_cont_phase_cal_r,
             rx_fast_cont_data_cal_r,
             rx_fast_cont_adapt_r,
             rx_fast_cont_cal_adapt_r
             }),
    .cr_rd_data(cr_fast_flags_2_rd_data),
    .cr_wr_data(cr_wr_data),
    .cr_wr_en(cr_wr_en),
    .cr_clk(cr_clk),
    .cr_rst(cr_rst_aon),
    .cr_sel(cr_sel_fast_flags_2),
    .cr_self_clr(1'b0)
);

// Mantis 6866 - Add override registers for tx/rx_disable signals
// %%CREG TXRX_OVRD_IN - Override values for incoming AON TX/RX controls from PCS
//   OFFSET: 0x30
//   ATTR:   RW, CUST
//   FIELDS:
//       [3] TX_DISABLE_OVRD_EN      - Override enable for tx_disable
//           RESET: 0x0
//       [2] TX_DISABLE_OVRD_VAL     - Override value for tx_disable
//           RESET: 0x0
//       [1] RX_DISABLE_OVRD_EN      - Override enable for rx_disable
//           RESET: 0x0
//       [0] RX_DISABLE_OVRD_VAL     - Override value for rx_disable
//           RESET: 0x0
wire        tx_disable_ovrd_en;
wire        tx_disable_ovrd_val;
wire        rx_disable_ovrd_en;
wire        rx_disable_ovrd_val;
wire        cr_sel_txrx_ovrd_in = cr_lane_aon_sel2[16];
wire [15:0] cr_txrx_ovrd_in_rd_data;
dwc_e12mp_phy_x4_ns_cr_rw_reg #(.WIDTH(4), .RST_VAL(4'b00_00), .MSK_VAL(4'd0))
  txrx_ovrd_in_reg (
    .cr_val({
             tx_disable_ovrd_en,
             tx_disable_ovrd_val,
             rx_disable_ovrd_en,
             rx_disable_ovrd_val
             }),
    .cr_rd_data(cr_txrx_ovrd_in_rd_data),
    .cr_wr_data(cr_wr_data),
    .cr_wr_en(cr_wr_en),
    .cr_clk(cr_clk),
    .cr_rst(cr_rst_aon),
    .cr_sel(cr_sel_txrx_ovrd_in),
    .cr_self_clr(1'b0)
);

`ifdef DWC_E12MP_X4NS_RX_CDR_PPM_DETECTOR_ADDED
// %%CREG RX_CDR_DETECTOR_CTL - RX CDR Detector Control 
//   OFFSET: 0x31
//   ATTR:   RW
//   FIELDS:
//      [2] DIS_IN_ADAPT              - Disable the CDR Detector state machine for during adaptation
//          RESET: 0x1
//      [1] RX_CDR_PPM_MONITOR_MODE   - Enable the CDR Detector in Monitor Mode. 
//          RESET: 0x0                 
//          NOTES:                     To enable monitor mode only, disable
//                                     detector mode and set this field
//      [0] RX_CDR_DETECTOR_EN        - Enable the CDR Detector in Detector Mode. 
//          RESET: 0x1                 
//          NOTES:                     In detector mode, monitor mode is also enabled
//
wire        cr_sel_rx_cdr_detector_ctl = cr_lane_aon_sel2[17];
wire [15:0] cr_rx_cdr_detector_ctl_rd_data;
dwc_e12mp_phy_x4_ns_cr_rw_reg #(.WIDTH(3), .RST_VAL(3'b1_0_1), .MSK_VAL(3'd0))
  rx_cdr_detector_ctl_reg (
    .cr_val({
             rx_cdr_detector_dis_in_adapt_r,
             rx_cdr_ppm_monitor_mode_r,
             rx_cdr_detector_en_r
             }),
    .cr_rd_data(cr_rx_cdr_detector_ctl_rd_data),
    .cr_wr_data(cr_wr_data),
    .cr_wr_en(cr_wr_en),
    .cr_clk(cr_clk),
    .cr_rst(cr_rst_aon),
    .cr_sel(cr_sel_rx_cdr_detector_ctl),
    .cr_self_clr(1'b0)
);


// %%CREG RX_CDR_RECOVERY_TIME - RX CDR Recovery Time in reference clock for the intended PPM
//   OFFSET: 0x32
//   ATTR:   RW
//   FIELDS:
//    [11:0] RX_CDR_RECOVERY_TIME       - RX CDR Recovery Time in reference clock for intended PPM
//           RESET: 0x585                       
//           NOTES:                             this default CDR Recovery Time is determined based 
//                                              on 15000 ppm drift on serial data. This value corresponds 
//                                              to the rxX_cdr_ppm_max input which is also calculated to
//                                              detect 15000 ppm on serial data
// 
wire        cr_sel_rx_cdr_recovery_time = cr_lane_aon_sel2[18];
wire [15:0] cr_rx_cdr_recovery_time_rd_data;
dwc_e12mp_phy_x4_ns_cr_rw_reg #(.WIDTH(12), .RST_VAL(12'd1413), .MSK_VAL(12'd0))
  rx_cdr_recovery_time_reg (
    .cr_val({
             rx_cdr_recovery_time_r
             }),
    .cr_rd_data(cr_rx_cdr_recovery_time_rd_data),
    .cr_wr_data(cr_wr_data),
    .cr_wr_en(cr_wr_en),
    .cr_clk(cr_clk),
    .cr_rst(cr_rst_aon),
    .cr_sel(cr_sel_rx_cdr_recovery_time),
    .cr_self_clr(1'b0)
);
`endif

// Override for tx_disable
wire tx_disable_i;
dwc_e12mp_phy_x4_ns_asic_in tx_disable_in (
  .asic           (tx_disable),
  .phy            (tx_disable_i),
  .clk            (1'b0),
  .rst            (1'b0),
  .test_ovrd      (1'b0),
  .test_ovrd_val  (1'b0),
  .cr_ovrd        (tx_disable_ovrd_en),
  .cr_ovrd_val    (tx_disable_ovrd_val)
);

// Override for rx_disable
wire rx_disable_i;
dwc_e12mp_phy_x4_ns_asic_in rx_disable_in (
  .asic           (rx_disable),
  .phy            (rx_disable_i),
  .clk            (1'b0),
  .rst            (1'b0),
  .test_ovrd      (1'b0),
  .test_ovrd_val  (1'b0),
  .cr_ovrd        (rx_disable_ovrd_en),
  .cr_ovrd_val    (rx_disable_ovrd_val)
);

// Add this lane's disable to daisy chain
assign lane_disable_out = tx_disable_i & rx_disable_i & lane_disable_in;

// Output the disable signals to the PMA
assign tx_pma_disable = tx_disable_i;
assign rx_pma_disable = rx_disable_i;

// Mux in the CREG cr_rd_data
assign cr_lane_aon_rd_data =   cr_afe_att_idac_ofst_rd_data
                             | cr_afe_ctle_idac_ofst_rd_data
                             | cr_afe_vga1_idac_ofst_rd_data
                             | cr_dfe_sume_idac_ofst_rd_data
                             | cr_dfe_sumo_idac_ofst_rd_data
                             | cr_phase_even_vdac_ofst_rd_data
                             | cr_phase_odd_vdac_ofst_rd_data
                             | cr_phase_even_low_vdac_ofst_rd_data
                             | cr_phase_odd_low_vdac_ofst_rd_data
                             | cr_rx_phsadj_lin_rd_data
                             | cr_rx_phsadj_map_rd_data
                             | cr_dfe_t1eh_vdac_ofst_rd_data
                             | cr_dfe_t1el_vdac_ofst_rd_data
                             | cr_dfe_t1oh_vdac_ofst_rd_data
                             | cr_dfe_t1ol_vdac_ofst_rd_data
                             | cr_dfe_bype_vdac_ofst_rd_data
                             | cr_dfe_bypo_vdac_ofst_rd_data
                             | cr_dfe_erre_vdac_ofst_rd_data
                             | cr_dfe_erro_vdac_ofst_rd_data
                             | cr_rx_iq_phase_adjust_rd_data
                             | cr_mplla_coarse_tune_rd_data
                             | cr_mpllb_coarse_tune_rd_data
                             | cr_rtune_rx_val_rd_data
                             | cr_rtune_txdn_val_rd_data
                             | cr_rtune_txup_val_rd_data
                             | cr_init_pwrup_done_rd_data
                             | cr_rx_att_adpt_val_rd_data
                             | cr_rx_vga_adpt_val_rd_data
                             | cr_rx_ctle_adpt_val_rd_data
                             | cr_rx_dfe_tap1_adpt_val_rd_data
                             | cr_rx_adpt_done_rd_data
                             | cr_fast_flags_rd_data
                             | cr_rx_dfe_tap2_adpt_val_rd_data
                             | cr_rx_dfe_tap3_adpt_val_rd_data
                             | cr_rx_dfe_tap4_adpt_val_rd_data
                             | cr_rx_dfe_tap5_adpt_val_rd_data
                             | cr_rx_slicer_ctrl_e_rd_data
                             | cr_rx_slicer_ctrl_o_rd_data
                             | cr_cmncal_sts_rd_data
                             | cr_adpt_ctl_0_rd_data
                             | cr_adpt_ctl_1_rd_data
                             | cr_adpt_ctl_2_rd_data
                             | cr_adpt_ctl_3_rd_data
                             | cr_adpt_ctl_4_rd_data
                             | cr_adpt_ctl_5_rd_data
                             | cr_adpt_ctl_6_rd_data
                             | cr_adpt_ctl_7_rd_data
                             | cr_fast_flags_2_rd_data
`ifdef DWC_E12MP_X4NS_RX_CDR_PPM_DETECTOR_ADDED
                             | cr_txrx_ovrd_in_rd_data
                             | cr_rx_cdr_detector_ctl_rd_data
                             | cr_rx_cdr_recovery_time_rd_data;
`else
                             | cr_txrx_ovrd_in_rd_data;
`endif

endmodule
